/ -- Highlights:
Cadence delivers 7nm digital implementation and signoff RAK for the development of Arm Neoverse N1-based designs
Cadence Verification Suite and its engines enhance verification throughput for engineers creating Neoverse N1-based designs
Cadence DDR4 PHY IP, CCIX IP, and PCIe 4.0 PHY IP integrated and with Neoverse N1 SoC, driving key I/O interfaces to peak levels of performance
Arm Neoverse N1 System Design Platform and board based on Neoverse N1 platform and Cadence IP was implemented and verified using Cadence tools in support of CCIX cache coherency for asymmetrical compute acceleration
7nm Digital Implementation and Signoff RAK
More From This Section
Cadence Verification Suite
Neoverse N1 SDP
"The Neoverse N1 platform delivers the latest high-performance compute with optimal power consumption to support the diverse compute requirements of the next-generation infrastructure from hyperscale to edge access," said Drew Henry, senior vice president and general manager, Infrastructure Line of Business, Arm. "Through our continued collaboration with Cadence, customers can enhance their development environments to quickly differentiate themselves with their next-generation Neoverse-based solutions."
"We worked closely with Arm to optimize our advanced digital implementation and signoff solutions, the Cadence Verification Suite and our IP for the Neoverse N1 platform so our customers can efficiently create innovative 7nm designs," said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. "As part of this collaboration, Cadence provided tools and IP for the Arm Neoverse N1 SDP, and customers can begin designing Neoverse SDP-based systems immediately."
To further facilitate adoption of the Neoverse N1 platform, a series of seminars will be held during Q2 2019, where customers can learn how to implement the new processor using the Cadence tools and IP. Seminars are being planned in the following locations:
About Cadence