City firm releases nano chip design 'toolkit'

SoftJin Infotech, a software tools provider for semiconductor chip makers, has released 'Nirmaan'. The software toolkit that the firm says will improve the process of making designs of highly complex chips manufacturer-friendly.

This toolkit for chip design tool makers and chip designers addresses a potential multi-million dollar market, what the industry calls electronics design automation (EDA), SoftJin's senior executives say.

Nirmaan tackles the "challenges at the post-layout tool development stage of the sub-90 nanometre integrated chip manufacturing process," says Arvind Sadiappan, a SoftJin spokesperson.

A nanometre is a millionth of a metre and small wafers of silicon with millions of transistors built into them that are of the order of 90 nanometre are beginning to hit the market, Sadiappan says.

What this toolkit does is help designers make the software tools required to check the "final design" of a chip before it gets imprinted on to the silicon wafer.

At this stage and further, "it is not about electronics but geometrics". In other words, how to translate the plan of a chip to an actual chip that is laid out most efficiently.

Presently, the only alternative for post-layout EDA tool developers is to develop their own geometric data-organisation and geometrical operations, says Nachiket Urdhwareshe, SoftJin's chief executive officer.

"Nirmaan is the first offering in the market that provides a readymade, performance-tuned and customised tool kit for these developers," he says.

At 90 nanometre levels, the possibility that a design or parts of it will not be amenable to fabrication increases, he says. At this stage, Nirmaan will come in handy to ensure "design for manufacturability" (DFM) or "design for yield" (DFY), as the industry calls it.

For instance, a design may have two particular lines pretty close to each other, which if put into the manufacturing process may "violate" the rules of fabrication. So, "post-layout work can involve separating the two lines a bit more, or distorting the design just that bit, which after manufacturing brings the chip close to the designers' desired specifications," Sadiappan says.

The toolkit will help other "electronics design automation" (EDA) tool companies and in-house computer aided design groups of semiconductor companies to more effectively develop EDA tools. The current market size of post-layout EDA tools is estimated at some $500 million. SoftJin says the DFM/DFY tools as a segment of that market will grow much faster, to reach some $400 million for the segment alone by 2007.

Urdhwareshe says the development of customised DFM/DFY tools is an important and growing segment of the EDA market. "With our building blocks and services, Nirmaan reduces the overall cost of development and time to market for EDA tool makers."

Tool developers can now focus on their own USPs (unique selling propositions) rather than spending time and effort on essential but non-core aspects, he says.

Nirmaan can accelerate product development plans for companies developing new post layout tools, especially DFM/DFY products. Companies with existing post-layout EDA products can shift to Nirmaan as a platform to improve the performance and scalability of their products, he says.

Presently, only the large "volume players" like Intel, for its processors, and Altera, for its FPGA (field programmable gate array) chips are venturing into 90 nanometre, as the costs are high.

"For every 100 chips you make, some 60 will work well, as the manufacturing process is still being fine tuned. With the earlier 130 nm chips, yield could be as high as 95 per cent, as people have been making such chips for a few years now."