Chip design is a complex, design-intensive and time-consuming process. With chip complexity growing and with chips having hundreds of blocks sometimes, the time spent by designers and designer requirements have grown over the years.
San Jose-headquartered and Nasdaq listed Cadence Design Systems wants to change this with the recent launch of Cerebrus, a ML-based tool that automates and scales chip design.
“We have reinforced an ML engine that can improve the productivity of the design by 10x and we can bring in PPA (power, performance, area) improvement by 20 per cent. It provides an automated process from synthesis to sign-off,